1. Field of the Invention
The present invention relates to data processors having therein a plurality of counters controlled on a time division basis, and more specifically to data processors having therein a plurality of counter functions realized by a corresponding number of registers and controlled on a time division basis, which processors are capable of reading out a content of the registers with a high instruction execution efficiency.
2. Description of Related Art
Heretofore, in most of data processors having a plurality of counters therein, the plurality of counters are operated on a time division basis in order to save the number of necessary circuit elements, i.e., to elevate the use efficiency of circuits. More specifically, the counters are generally composed of a corresponding number of count registers associated with a common incrementer for sequentially incrementing the count registers one by one. Therefore, each of the respective count registers is accessible only at a predetermined time slot in which the content of the counter is incremented, i.e., at predetermined intervals. As a result, when the data processor wishes to read the content of any count registers, the data processor has to wait the reading of the count register until the time slot allotted to the count register to which the data processor wishes to access. This will decrease the instruction execution efficiency. In addition, the larger the number of the counters becomes, the larger the decrease of the instruction execution efficiency will become.